vhdl -UR
Experiment
2: Universal Shift Register
Roll no.:
Name :
----------------------------------------------------VHDL
CODE------------------------------------------------------------------
library IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
entity unishift
is
PORT(
Pin : in std_logic_vector(3 downto 0);
Pout: out std_logic_vector(3 downto 0);
mode: in std_logic_vector(1 downto 0); -- 01: Shift Left, 10: Shift
Right, 11: Parallel loading
clk,rst,Sin : in std_logic;
Sout : out std_logic
);
end unishift;
architecture
Behavioral of unishift is
signal tmp :
std_logic_vector(3 downto 0);
begin
process(clk,rst)
begin
if (rst = '1') then
tmp <=
"0000";
elsif
rising_edge(clk) then
if mode = "01" then
tmp(0)
<= Sin;
tmp(1)
<= tmp(0);
tmp(2)
<= tmp(1);
tmp(3)
<= tmp(2);
elsif mode = "10" then
tmp(3)
<= Sin;
tmp(2)
<= tmp(3);
tmp(1)
<= tmp(2);
tmp(0)
<= tmp(1);
elsif mode = "11" then
tmp <= Pin;
end if;
end if;
end process;
Pout <= tmp;
Sout <=
tmp(3);
end Behavioral;
----------------------------------------------------TEST
BENCH-----------------------------------------------------------------
LIBRARY ieee;
USE
ieee.std_logic_1164.ALL;
ENTITY test IS
END test;
ARCHITECTURE
behavior OF test IS
-- Component Declaration for the Unit Under
Test (UUT)
COMPONENT unishift
PORT(
Pin : IN std_logic_vector(3 downto 0);
Pout : OUT std_logic_vector(3 downto 0);
mode : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
rst : IN std_logic;
Sin : IN std_logic;
Sout : OUT std_logic
);
END COMPONENT;
--Inputs
signal Pin : std_logic_vector(3 downto 0) :=
(others => '0');
signal mode : std_logic_vector(1 downto 0)
:= (others => '0');
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal Sin : std_logic := '0';
--Outputs
signal Pout : std_logic_vector(3 downto 0);
signal Sout : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under
Test (UUT)
uut: unishift PORT MAP (
Pin => Pin,
Pout => Pout,
mode => mode,
clk => clk,
rst => rst,
Sin => Sin,
Sout => Sout
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for
clk_period/2;
clk <= '1';
wait for
clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 10 ns;
rst <= '0';
wait for 10 ns;
Pin <= "1011";
mode <= "11";
wait for 50 ns;
rst <= '1';
wait for 10 ns;
rst <= '0';
Pin <= "1001";
wait;
end process;
END;
-----------------------------------------------------
RTL SCHEMATIC-----------------------------------------------------------
-------------------------------------------------------
SIMULATION-------------------------------------------------------------
SISO:
SIPO:
PISO:
PIPO:
=========================================================================
* Design Summary *
=========================================================================
Top Level Output
File Name : unishift.ngc
Primitive and
Black Box Usage:
------------------------------
# BELS : 5
# LUT2 : 1
# LUT5 : 4
#
FlipFlops/Latches : 4
# FDCE : 4
# Clock
Buffers : 1
# BUFGP : 1
# IO Buffers : 12
# IBUF : 8
# OBUF : 4
Device
utilization summary:
---------------------------
Selected Device :
6slx9tqg144-2
Slice Logic
Utilization:
Number of Slice Registers: 4 out of
11440 0%
Number of Slice LUTs: 5 out of
5720 0%
Number used as Logic: 5 out of
5720 0%
Slice Logic
Distribution:
Number of LUT Flip Flop pairs used: 9
Number with an unused Flip Flop: 5
out of 9 55%
Number with an unused LUT: 4
out of 9 44%
Number of fully used LUT-FF pairs: 0
out of 9 0%
Number of unique control sets: 1
IO Utilization:
Number of IOs: 13
Number of bonded IOBs: 13 out of
102 12%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of
16 6%
---------------------------
Partition
Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE
TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE
REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock
Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF
name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 4 |
-----------------------------------+------------------------+-------+
Asynchronous
Control Signals Information:
----------------------------------------
No asynchronous
control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 1.683ns (Maximum Frequency:
594.177MHz)
Minimum input arrival time before clock:
3.632ns
Maximum output required time after clock:
4.202ns
Maximum combinational path delay: No path
found
Timing Details:
---------------
All values
displayed in nanoseconds (ns)
=========================================================================
Timing
constraint: Default period analysis for Clock 'clk'
Clock period: 1.683ns (frequency: 594.177MHz)
Total number of paths / destination ports: 6
/ 4
-------------------------------------------------------------------------
Delay: 1.683ns (Levels of Logic = 1)
Source: tmp_0 (FF)
Destination: tmp_1 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: tmp_0 to tmp_1
Gate Net
Cell:in->out fanout
Delay Delay Logical Name (Net Name)
----------------------------------------
------------
FDCE:C->Q 2
0.525 0.834 tmp_0 (tmp_0)
LUT5:I3->O 1
0.250 0.000 mux511 (tmp[3]_tmp[2]_mux_5_OUT<1>)
FDCE:D 0.074 tmp_1
----------------------------------------
Total 1.683ns (0.849ns logic,
0.834ns route)
(50.4%
logic, 49.6% route)
=========================================================================
Timing
constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 26
/ 12
-------------------------------------------------------------------------
Offset: 3.632ns (Levels of Logic = 2)
Source: mode<1> (PAD)
Destination: tmp_0 (FF)
Destination Clock: clk rising
Data Path: mode<1> to tmp_0
Gate Net
Cell:in->out fanout
Delay Delay Logical Name (Net Name)
----------------------------------------
------------
IBUF:I->O 5
1.328 0.949 mode_1_IBUF (mode_1_IBUF)
LUT2:I0->O 4
0.250 0.803 _n0025_inv1 (_n0025_inv)
FDCE:CE 0.302 tmp_0
----------------------------------------
Total 3.632ns (1.880ns logic,
1.752ns route)
(51.8%
logic, 48.2% route)
=========================================================================
Timing
constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 4
/ 4
-------------------------------------------------------------------------
Offset: 4.202ns (Levels of Logic = 1)
Source: tmp_2 (FF)
Destination: Pout<2> (PAD)
Source Clock: clk rising
Data Path: tmp_2 to Pout<2>
Gate Net
Cell:in->out fanout
Delay Delay Logical Name (Net Name)
----------------------------------------
------------
FDCE:C->Q 3
0.525 0.765 tmp_2 (tmp_2)
OBUF:I->O 2.912 Pout_2_OBUF (Pout<2>)
----------------------------------------
Total 4.202ns (3.437ns logic,
0.765ns route)
(81.8%
logic, 18.2% route)
=========================================================================
Cross Clock
Domains Report:
--------------------------
Clock to Setup on
destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise|
Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk |
1.683| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time
to Xst completion: 7.00 secs
Total CPU time to
Xst completion: 6.93 secs
-->
Total memory
usage is 221684 kilobytes
Number of
errors : 0 (
0 filtered)
Number of
warnings : 0 ( 0 filtered)
Number of
infos : 0 (
0 filtered)
